1 cpu used
compiler option: -O0 -mp
WARNING: Multiplexing events to project totals--inaccuracy possible
Summary for execution of ./false2_O0
Based on 250 MHz IP27
MIPS R10000 CPU
CPU revision 3.x
Typical Minimum Maximum
Event Counter Name Counter Value Time (sec) Time (sec) Time (sec)
===================================================================================================================
0 Cycles...................................................... 1196745712 4.786983 4.786983 4.786983
16 Cycles...................................................... 1196745712 4.786983 4.786983 4.786983
2 Issued loads................................................ 687681168 2.750725 2.750725 2.750725
14 ALU/FPU progress cycles..................................... 566585808 2.266343 2.266343 2.266343
18 Graduated loads............................................. 526799744 2.107199 2.107199 2.107199
3 Issued stores............................................... 82022400 0.328090 0.328090 0.328090
19 Graduated stores............................................ 82001920 0.328008 0.328008 0.328008
25 Primary data cache misses................................... 5099168 0.183774 0.057519 0.183774
21 Graduated floating point instructions....................... 42287776 0.169151 0.084576 8.795857
6 Decoded branches............................................ 41255504 0.165022 0.165022 0.165022
26 Secondary data cache misses................................. 23008 0.006948 0.004543 0.007731
9 Primary instruction cache misses............................ 39232 0.002828 0.000884 0.002828
23 TLB misses.................................................. 5680 0.001547 0.001547 0.001547
22 Quadwords written back from primary data cache.............. 89536 0.001379 0.001125 0.001594
10 Secondary instruction cache misses.......................... 4208 0.001271 0.000831 0.001414
7 Quadwords written back from scache.......................... 18304 0.000469 0.000310 0.000469
24 Mispredicted branches....................................... 10784 0.000061 0.000028 0.000225
4 Issued store conditionals................................... 3248 0.000013 0.000013 0.000013
20 Graduated store conditionals................................ 640 0.000003 0.000003 0.000003
31 Store/prefetch exclusive to shared block in scache.......... 16 0.000000 0.000000 0.000000
1 Issued instructions......................................... 1446062208 0.000000 0.000000 5.784249
5 Failed store conditionals................................... 0 0.000000 0.000000 0.000000
8 Correctable scache data array ECC errors.................... 0 0.000000 0.000000 0.000000
11 Instruction misprediction from scache way prediction table.. 4880 0.000000 0.000000 0.000020
12 External interventions...................................... 2512 0.000000 0.000000 0.000000
13 External invalidations...................................... 54080 0.000000 0.000000 0.000000
15 Graduated instructions...................................... 1511573584 0.000000 0.000000 6.046294
17 Graduated instructions...................................... 563236848 0.000000 0.000000 2.252947
27 Data misprediction from scache way prediction table......... 244160 0.000000 0.000000 0.000977
28 External intervention hits in scache........................ 2400 0.000000 0.000000 0.000000
29 External invalidation hits in scache........................ 2624 0.000000 0.000000 0.000000
30 Store/prefetch exclusive to clean block in scache........... 0 0.000000 0.000000 0.000000
Statistics
=========================================================================================
Graduated instructions/cycle................................................ 1.263070
Graduated floating point instructions/cycle................................. 0.035336
Graduated loads & stores/cycle.............................................. 0.508714
Graduated loads & stores/floating point instruction......................... 14.396635
Mispredicted branches/Decoded branches...................................... 0.000261
Graduated loads/Issued loads................................................ 0.766052
Graduated stores/Issued stores.............................................. 0.999750
Data mispredict/Data scache hits............................................ 0.048099
Instruction mispredict/Instruction scache hits.............................. 0.139333
L1 Cache Line Reuse......................................................... 118.392353
L2 Cache Line Reuse......................................................... 220.625869
L1 Data Cache Hit Rate...................................................... 0.991624
L2 Data Cache Hit Rate...................................................... 0.995488
Time accessing memory/Total time............................................ 0.548879
Time not making progress (probably waiting on memory) / Total time.......... 0.526561
L1--L2 bandwidth used (MB/s, average per process)........................... 34.386159
Memory bandwidth used (MB/s, average per process)........................... 0.676394
MFLOPS (average per process)................................................ 8.833910
real 4.927
user 4.843
sys 0.037