2 cpus used
compiler option : -O0 -mp
WARNING: Multiplexing events to project totals--inaccuracy possible
Summary for execution of ./false2_O0
Based on 250 MHz IP27
MIPS R10000 CPU
CPU revision 3.x
Typical Minimum Maximum
Event Counter Name Counter Value Time (sec) Time (sec) Time (sec)
===================================================================================================================
0 Cycles...................................................... 8294020016 33.176080 33.176080 33.176080
16 Cycles...................................................... 8294020016 33.176080 33.176080 33.176080
26 Secondary data cache misses................................. 12983088 3.920893 2.563381 4.362318
2 Issued loads................................................ 824553120 3.298212 3.298212 3.298212
14 ALU/FPU progress cycles..................................... 685817728 2.743271 2.743271 2.743271
18 Graduated loads............................................. 679758240 2.719033 2.719033 2.719033
7 Quadwords written back from scache.......................... 103933568 2.660699 1.758556 2.660699
25 Primary data cache misses................................... 44020352 1.586493 0.496550 1.586493
22 Quadwords written back from primary data cache.............. 26457120 0.407440 0.332301 0.470937
3 Issued stores............................................... 92892416 0.371570 0.371570 0.371570
19 Graduated stores............................................ 80834624 0.323338 0.323338 0.323338
6 Decoded branches............................................ 42358032 0.169432 0.169432 0.169432
21 Graduated floating point instructions....................... 42047712 0.168191 0.084095 8.745924
31 Store/prefetch exclusive to shared block in scache.......... 11877264 0.047509 0.047509 0.047509
9 Primary instruction cache misses............................ 40432 0.002914 0.000911 0.002914
23 TLB misses.................................................. 2224 0.000606 0.000606 0.000606
10 Secondary instruction cache misses.......................... 1424 0.000430 0.000281 0.000478
24 Mispredicted branches....................................... 26512 0.000151 0.000068 0.000554
4 Issued store conditionals................................... 2400 0.000010 0.000010 0.000010
20 Graduated store conditionals................................ 464 0.000002 0.000002 0.000002
30 Store/prefetch exclusive to clean block in scache........... 16 0.000000 0.000000 0.000000
1 Issued instructions......................................... 1710831200 0.000000 0.000000 6.843325
5 Failed store conditionals................................... 0 0.000000 0.000000 0.000000
8 Correctable scache data array ECC errors.................... 0 0.000000 0.000000 0.000000
11 Instruction misprediction from scache way prediction table.. 16832 0.000000 0.000000 0.000067
12 External interventions...................................... 12967328 0.000000 0.000000 0.000000
13 External invalidations...................................... 6033104 0.000000 0.000000 0.000000
15 Graduated instructions...................................... 1518661888 0.000000 0.000000 6.074648
17 Graduated instructions...................................... 1520843744 0.000000 0.000000 6.083375
27 Data misprediction from scache way prediction table......... 118528 0.000000 0.000000 0.000474
28 External intervention hits in scache........................ 12966832 0.000000 0.000000 0.000000
29 External invalidation hits in scache........................ 5992896 0.000000 0.000000 0.000000
Statistics
=========================================================================================
Graduated instructions/cycle................................................ 0.183103
Graduated floating point instructions/cycle................................. 0.005070
Graduated loads & stores/cycle.............................................. 0.091704
Graduated loads & stores/floating point instruction......................... 18.088805
Mispredicted branches/Decoded branches...................................... 0.000626
Graduated loads/Issued loads................................................ 0.824396
Graduated stores/Issued stores.............................................. 0.870196
Data mispredict/Data scache hits............................................ 0.003819
Instruction mispredict/Instruction scache hits.............................. 0.431501
L1 Cache Line Reuse......................................................... 16.278209
L2 Cache Line Reuse......................................................... 2.390592
L1 Data Cache Hit Rate...................................................... 0.942124
L2 Data Cache Hit Rate...................................................... 0.705066
Time accessing memory/Total time............................................ 0.257727
Time not making progress (probably waiting on memory) / Total time.......... 0.917312
L1--L2 bandwidth used (MB/s, average per process)........................... 55.219459
Memory bandwidth used (MB/s, average per process)........................... 100.215949
MFLOPS (average per process)................................................ 1.267410
real 17.170
user 33.927
sys 0.048