Mchine used : Delilah, 300MHz, 8MB L2 cache, R12000
4 cpus used
compiler option: -O0 -mp
process 85951
WARNING: Multiplexing events to project totals--inaccuracy possible
Based on 300 MHz IP27
MIPS R12000/R14000 CPU
Costs for pid 85951 (false2_O0) Typical Minimum Maximum
Event Counter Name Counter Value Time (sec) Time (sec) Time (sec)
===================================================================================================================
0 Cycles...................................................... 6272336672 20.907789 20.907789 20.907789
16 Executed prefetch instructions.............................. 0 0.000000 0.000000 0.000000
4 Miss handling table occupancy............................... 6288212624 20.960709 20.960709 20.960709
26 Secondary data cache misses................................. 17385120 5.788665 3.652614 5.788665
2 Decoded loads............................................... 446693696 1.488979 1.488979 1.488979
18 Graduated loads............................................. 330850096 1.102834 1.102834 1.102834
7 Quadwords written back from scache.......................... 34867840 0.986760 0.685734 1.019303
6 Resolved conditional branches............................... 193399296 0.644664 0.644664 0.644664
25 Primary data cache misses................................... 14715392 0.416936 0.106441 0.416936
22 Quadwords written back from primary data cache.............. 8102752 0.107497 0.084809 0.107497
3 Decoded stores.............................................. 20618736 0.068729 0.068729 0.068729
19 Graduated stores............................................ 20201216 0.067337 0.067337 0.067337
21 Graduated floating point instructions....................... 10481376 0.034938 0.017469 1.816772
31 Store/prefetch exclusive to shared block in scache.......... 4110160 0.013701 0.013701 0.013701
10 Secondary instruction cache misses.......................... 1056 0.000352 0.000222 0.000352
9 Primary instruction cache misses............................ 5072 0.000288 0.000073 0.000288
23 TLB misses.................................................. 688 0.000178 0.000178 0.000178
24 Mispredicted branches....................................... 640 0.000016 0.000013 0.000019
1 Decoded instructions........................................ 1833956528 0.000000 0.000000 6.113188
5 Failed store conditionals................................... 0 0.000000 0.000000 0.000000
8 Correctable scache data array ECC errors.................... 0 0.000000 0.000000 0.000000
11 Instruction misprediction from scache way prediction table.. 976 0.000000 0.000000 0.000003
12 External interventions...................................... 5188736 0.000000 0.000000 0.000000
13 External invalidations...................................... 1659104 0.000000 0.000000 0.000000
14 ALU/FPU progress cycles..................................... 0 0.000000 0.000000 0.000000
15 Graduated instructions...................................... 619715952 0.000000 0.000000 2.065720
17 Prefetch primary data cache misses.......................... 0 0.000000 0.000000 0.000000
20 Graduated store conditionals................................ 0 0.000000 0.000000 0.000000
27 Data misprediction from scache way prediction table......... 326656 0.000000 0.000000 0.001089
28 State of intervention hits in scache........................ 5188736 0.000000 0.000000 0.000000
29 State of invalidation hits in scache........................ 1634320 0.000000 0.000000 0.000000
30 Store/prefetch exclusive to clean block in scache........... 0 0.000000 0.000000 0.000000
Statistics
=========================================================================================
Graduated instructions/cycle................................................ 0.098801
Graduated floating point instructions/cycle................................. 0.001671
Graduated loads & stores/cycle.............................................. 0.055968
Graduated loads & stores/floating point instruction......................... 33.492865
Mispredicted branches/Resolved conditional branches......................... 0.000003
Graduated loads /Decoded loads ( and prefetches )........................... 0.740664
Graduated stores/Decoded stores............................................. 0.979750
Instruction mispredict/Instruction scache hits.............................. 0.243028
L1 Cache Line Reuse......................................................... 22.856063
L2 Cache Line Reuse......................................................... -0.153564
L1 Data Cache Hit Rate...................................................... 0.958082
L2 Data Cache Hit Rate...................................................... -0.181424
Time accessing memory/Total time............................................ 0.352785
L1--L2 bandwidth used (MB/s, average per process)........................... 28.723103
Memory bandwidth used (MB/s, average per process)........................... 133.116936
MFLOPS (average per process)................................................ 0.501314
Cache misses in flight per cycle (average).................................. 1.002531
Prefetch cache miss rate.................................................... nan0x7fffffff
process 85952
Based on 300 MHz IP27
MIPS R12000/R14000 CPU
Costs for pid 85952 (false2_O0) Typical Minimum Maximum
Event Counter Name Counter Value Time (sec) Time (sec) Time (sec)
===================================================================================================================
0 Cycles...................................................... 5213026400 17.376755 17.376755 17.376755
16 Executed prefetch instructions.............................. 0 0.000000 0.000000 0.000000
4 Miss handling table occupancy............................... 5011984192 16.706614 16.706614 16.706614
26 Secondary data cache misses................................. 13373536 4.452942 2.809780 4.452942
2 Decoded loads............................................... 416542992 1.388477 1.388477 1.388477
18 Graduated loads............................................. 304559072 1.015197 1.015197 1.015197
6 Resolved conditional branches............................... 254085552 0.846952 0.846952 0.846952
7 Quadwords written back from scache.......................... 27957120 0.791186 0.549823 0.817280
25 Primary data cache misses................................... 14002416 0.396735 0.101284 0.396735
22 Quadwords written back from primary data cache.............. 7780736 0.103224 0.081438 0.103224
3 Decoded stores.............................................. 19651680 0.065506 0.065506 0.065506
19 Graduated stores............................................ 19347984 0.064493 0.064493 0.064493
21 Graduated floating point instructions....................... 9284800 0.030949 0.015475 1.609365
31 Store/prefetch exclusive to shared block in scache.......... 2984944 0.009950 0.009950 0.009950
9 Primary instruction cache misses............................ 9888 0.000561 0.000143 0.000561
23 TLB misses.................................................. 384 0.000100 0.000100 0.000100
24 Mispredicted branches....................................... 336 0.000008 0.000007 0.000010
1 Decoded instructions........................................ 1176085552 0.000000 0.000000 3.920285
5 Failed store conditionals................................... 0 0.000000 0.000000 0.000000
8 Correctable scache data array ECC errors.................... 0 0.000000 0.000000 0.000000
10 Secondary instruction cache misses.......................... 0 0.000000 0.000000 0.000000
11 Instruction misprediction from scache way prediction table.. 1440 0.000000 0.000000 0.000005
12 External interventions...................................... 3812544 0.000000 0.000000 0.000000
13 External invalidations...................................... 1872448 0.000000 0.000000 0.000000
14 ALU/FPU progress cycles..................................... 0 0.000000 0.000000 0.000000
15 Graduated instructions...................................... 606801776 0.000000 0.000000 2.022673
17 Prefetch primary data cache misses.......................... 0 0.000000 0.000000 0.000000
20 Graduated store conditionals................................ 0 0.000000 0.000000 0.000000
27 Data misprediction from scache way prediction table......... 578928 0.000000 0.000000 0.001930
28 State of intervention hits in scache........................ 3812544 0.000000 0.000000 0.000000
29 State of invalidation hits in scache........................ 1805648 0.000000 0.000000 0.000000
30 Store/prefetch exclusive to clean block in scache........... 0 0.000000 0.000000 0.000000
Statistics
=========================================================================================
Graduated instructions/cycle................................................ 0.116401
Graduated floating point instructions/cycle................................. 0.001781
Graduated loads & stores/cycle.............................................. 0.062134
Graduated loads & stores/floating point instruction......................... 34.885733
Mispredicted branches/Resolved conditional branches......................... 0.000001
Graduated loads /Decoded loads ( and prefetches )........................... 0.731159
Graduated stores/Decoded stores............................................. 0.984546
Data mispredict/Data scache hits............................................ 0.920570
Instruction mispredict/Instruction scache hits.............................. 0.145631
L1 Cache Line Reuse......................................................... 22.132226
L2 Cache Line Reuse......................................................... 0.047024
L1 Data Cache Hit Rate...................................................... 0.956770
L2 Data Cache Hit Rate...................................................... 0.044912
Time accessing memory/Total time............................................ 0.341230
L1--L2 bandwidth used (MB/s, average per process)........................... 32.950289
Memory bandwidth used (MB/s, average per process)........................... 124.253727
MFLOPS (average per process)................................................ 0.534323
Cache misses in flight per cycle (average).................................. 0.961435
Prefetch cache miss rate.................................................... nan0x7fffffff
process 85954
Based on 300 MHz IP27
MIPS R12000/R14000 CPU
Costs for pid 85954 (false2_O0) Typical Minimum Maximum
Event Counter Name Counter Value Time (sec) Time (sec) Time (sec)
===================================================================================================================
0 Cycles...................................................... 6275315264 20.917718 20.917718 20.917718
16 Executed prefetch instructions.............................. 0 0.000000 0.000000 0.000000
4 Miss handling table occupancy............................... 5062774768 16.875916 16.875916 16.875916
6 Resolved conditional branches............................... 1137718864 3.792396 3.792396 3.792396
2 Decoded loads............................................... 1038214752 3.460716 3.460716 3.460716
26 Secondary data cache misses................................. 9585440 3.191632 2.013901 3.191632
18 Graduated loads............................................. 904076640 3.013589 3.013589 3.013589
7 Quadwords written back from scache.......................... 17301568 0.489634 0.340264 0.505783
25 Primary data cache misses................................... 10718720 0.303697 0.077532 0.303697
3 Decoded stores.............................................. 21196544 0.070655 0.070655 0.070655
19 Graduated stores............................................ 20553152 0.068511 0.068511 0.068511
22 Quadwords written back from primary data cache.............. 4279936 0.056780 0.044797 0.056780
21 Graduated floating point instructions....................... 9923568 0.033079 0.016539 1.720085
31 Store/prefetch exclusive to shared block in scache.......... 2113168 0.007044 0.007044 0.007044
23 TLB misses.................................................. 1552 0.000402 0.000402 0.000402
9 Primary instruction cache misses............................ 4832 0.000274 0.000070 0.000274
24 Mispredicted branches....................................... 1088 0.000026 0.000022 0.000032
1 Decoded instructions........................................ 3124101264 0.000000 0.000000 10.413671
5 Failed store conditionals................................... 0 0.000000 0.000000 0.000000
8 Correctable scache data array ECC errors.................... 0 0.000000 0.000000 0.000000
10 Secondary instruction cache misses.......................... 0 0.000000 0.000000 0.000000
11 Instruction misprediction from scache way prediction table.. 1264 0.000000 0.000000 0.000004
12 External interventions...................................... 2442112 0.000000 0.000000 0.000000
13 External invalidations...................................... 2362544 0.000000 0.000000 0.000000
14 ALU/FPU progress cycles..................................... 0 0.000000 0.000000 0.000000
15 Graduated instructions...................................... 2350005216 0.000000 0.000000 7.833351
17 Prefetch primary data cache misses.......................... 0 0.000000 0.000000 0.000000
20 Graduated store conditionals................................ 0 0.000000 0.000000 0.000000
27 Data misprediction from scache way prediction table......... 3336608 0.000000 0.000000 0.011122
28 State of intervention hits in scache........................ 2442112 0.000000 0.000000 0.000000
29 State of invalidation hits in scache........................ 1912400 0.000000 0.000000 0.000000
30 Store/prefetch exclusive to clean block in scache........... 0 0.000000 0.000000 0.000000
Statistics
=========================================================================================
Graduated instructions/cycle................................................ 0.374484
Graduated floating point instructions/cycle................................. 0.001581
Graduated loads & stores/cycle.............................................. 0.147344
Graduated loads & stores/floating point instruction......................... 93.175135
Mispredicted branches/Resolved conditional branches......................... 0.000001
Graduated loads /Decoded loads ( and prefetches )........................... 0.870799
Graduated stores/Decoded stores............................................. 0.969646
Data mispredict/Data scache hits............................................ 2.944204
Instruction mispredict/Instruction scache hits.............................. 0.261589
L1 Cache Line Reuse......................................................... 85.263079
L2 Cache Line Reuse......................................................... 0.118229
L1 Data Cache Hit Rate...................................................... 0.988408
L2 Data Cache Hit Rate...................................................... 0.105729
Time accessing memory/Total time............................................ 0.314462
L1--L2 bandwidth used (MB/s, average per process)........................... 19.671267
Memory bandwidth used (MB/s, average per process)........................... 71.889364
MFLOPS (average per process)................................................ 0.474410
Cache misses in flight per cycle (average).................................. 0.806776
Prefetch cache miss rate.................................................... nan0x7fffffff
process 85882
Based on 300 MHz IP27
MIPS R12000/R14000 CPU
Costs for pid 85882 (false2_O0) Typical Minimum Maximum
Event Counter Name Counter Value Time (sec) Time (sec) Time (sec)
===================================================================================================================
0 Cycles...................................................... 5217413584 17.391379 17.391379 17.391379
16 Executed prefetch instructions.............................. 2784 0.000000 0.000000 0.000000
4 Miss handling table occupancy............................... 4833923088 16.113077 16.113077 16.113077
26 Secondary data cache misses................................. 9425856 3.138496 1.980372 3.138496
2 Decoded loads............................................... 314688704 1.048962 1.048962 1.048962
18 Graduated loads............................................. 174602320 0.582008 0.582008 0.582008
7 Quadwords written back from scache.......................... 14896128 0.421560 0.292957 0.435463
25 Primary data cache misses................................... 9077024 0.257182 0.065657 0.257182
6 Resolved conditional branches............................... 26186240 0.087287 0.087287 0.087287
3 Decoded stores.............................................. 20708000 0.069027 0.069027 0.069027
19 Graduated stores............................................ 20265536 0.067552 0.067552 0.067552
22 Quadwords written back from primary data cache.............. 4778080 0.063389 0.050011 0.063389
21 Graduated floating point instructions....................... 10472416 0.034908 0.017454 1.815219
31 Store/prefetch exclusive to shared block in scache.......... 1928464 0.006428 0.006428 0.006428
9 Primary instruction cache misses............................ 39280 0.002227 0.000568 0.002227
24 Mispredicted branches....................................... 18784 0.000456 0.000376 0.000552
10 Secondary instruction cache misses.......................... 1264 0.000421 0.000266 0.000421
23 TLB misses.................................................. 928 0.000241 0.000241 0.000241
20 Graduated store conditionals................................ 272 0.000001 0.000001 0.000001
30 Store/prefetch exclusive to clean block in scache........... 192 0.000001 0.000001 0.000001
1 Decoded instructions........................................ 687550880 0.000000 0.000000 2.291836
5 Failed store conditionals................................... 0 0.000000 0.000000 0.000000
8 Correctable scache data array ECC errors.................... 0 0.000000 0.000000 0.000000
11 Instruction misprediction from scache way prediction table.. 1024 0.000000 0.000000 0.000003
12 External interventions...................................... 2225136 0.000000 0.000000 0.000000
13 External invalidations...................................... 1606816 0.000000 0.000000 0.000000
14 ALU/FPU progress cycles..................................... 0 0.000000 0.000000 0.000000
15 Graduated instructions...................................... 374222368 0.000000 0.000000 1.247408
17 Prefetch primary data cache misses.......................... 512 0.000000 0.000000 0.000002
27 Data misprediction from scache way prediction table......... 2041504 0.000000 0.000000 0.006805
28 State of intervention hits in scache........................ 2224992 0.000000 0.000000 0.000000
29 State of invalidation hits in scache........................ 1596000 0.000000 0.000000 0.000000
Statistics
=========================================================================================
Graduated instructions/cycle................................................ 0.071726
Graduated floating point instructions/cycle................................. 0.002007
Graduated loads & stores/cycle.............................................. 0.037350
Graduated loads & stores/floating point instruction......................... 18.607727
Mispredicted branches/Resolved conditional branches......................... 0.000717
Graduated loads /Decoded loads ( and prefetches )........................... 0.554836
Graduated stores/Decoded stores............................................. 0.978633
Instruction mispredict/Instruction scache hits.............................. 0.026936
L1 Cache Line Reuse......................................................... 20.468254
L2 Cache Line Reuse......................................................... -0.037008
L1 Data Cache Hit Rate...................................................... 0.953420
L2 Data Cache Hit Rate...................................................... -0.038430
Time accessing memory/Total time............................................ 0.232614
L1--L2 bandwidth used (MB/s, average per process)........................... 21.097468
Memory bandwidth used (MB/s, average per process)........................... 83.078383
MFLOPS (average per process)................................................ 0.602161
Cache misses in flight per cycle (average).................................. 0.926498
Prefetch cache miss rate.................................................... 0.183908
aggregrated data from all processes
Summary for execution of ./false2_O0
Based on 300 MHz IP27
MIPS R12000/R14000 CPU
Typical Minimum Maximum
Event Counter Name Counter Value Time (sec) Time (sec) Time (sec)
===================================================================================================================
0 Cycles...................................................... 22978641392 76.595471 76.595471 76.595471
16 Executed prefetch instructions.............................. 2784 0.000000 0.000000 0.000000
4 Miss handling table occupancy............................... 21196894672 70.656316 70.656316 70.656316
26 Secondary data cache misses................................. 49769952 16.571735 10.456667 16.571735
2 Decoded loads............................................... 2216140144 7.387134 7.387134 7.387134
18 Graduated loads............................................. 1714088128 5.713627 5.713627 5.713627
6 Resolved conditional branches............................... 1611389952 5.371300 5.371300 5.371300
7 Quadwords written back from scache.......................... 95022656 2.689141 1.868779 2.777829
25 Primary data cache misses................................... 48513552 1.374551 0.350915 1.374551
22 Quadwords written back from primary data cache.............. 24941504 0.330891 0.261054 0.330891
3 Decoded stores.............................................. 82174960 0.273917 0.273917 0.273917
19 Graduated stores............................................ 80367888 0.267893 0.267893 0.267893
21 Graduated floating point instructions....................... 40162160 0.133874 0.066937 6.961441
31 Store/prefetch exclusive to shared block in scache.......... 11136736 0.037122 0.037122 0.037122
9 Primary instruction cache misses............................ 59072 0.003349 0.000855 0.003349
23 TLB misses.................................................. 3552 0.000921 0.000921 0.000921
10 Secondary instruction cache misses.......................... 2320 0.000772 0.000487 0.000772
24 Mispredicted branches....................................... 20848 0.000506 0.000417 0.000612
20 Graduated store conditionals................................ 272 0.000001 0.000001 0.000001
30 Store/prefetch exclusive to clean block in scache........... 192 0.000001 0.000001 0.000001
1 Decoded instructions........................................ 6821694224 0.000000 0.000000 22.738981
5 Failed store conditionals................................... 0 0.000000 0.000000 0.000000
8 Correctable scache data array ECC errors.................... 0 0.000000 0.000000 0.000000
11 Instruction misprediction from scache way prediction table.. 4704 0.000000 0.000000 0.000016
12 External interventions...................................... 13668528 0.000000 0.000000 0.000000
13 External invalidations...................................... 7500912 0.000000 0.000000 0.000000
14 ALU/FPU progress cycles..................................... 0 0.000000 0.000000 0.000000
15 Graduated instructions...................................... 3950745312 0.000000 0.000000 13.169151
17 Prefetch primary data cache misses.......................... 512 0.000000 0.000000 0.000002
27 Data misprediction from scache way prediction table......... 6283696 0.000000 0.000000 0.020946
28 State of intervention hits in scache........................ 13668384 0.000000 0.000000 0.000000
29 State of invalidation hits in scache........................ 6948368 0.000000 0.000000 0.000000
Statistics
=========================================================================================
Graduated instructions/cycle................................................ 0.171931
Graduated floating point instructions/cycle................................. 0.001748
Graduated loads & stores/cycle.............................................. 0.078092
Graduated loads & stores/floating point instruction......................... 44.680267
Mispredicted branches/Resolved conditional branches......................... 0.000013
Graduated loads /Decoded loads ( and prefetches )........................... 0.773456
Graduated stores/Decoded stores............................................. 0.978009
Instruction mispredict/Instruction scache hits.............................. 0.082887
L1 Cache Line Reuse......................................................... 35.988758
L2 Cache Line Reuse......................................................... -0.025244
L1 Data Cache Hit Rate...................................................... 0.972965
L2 Data Cache Hit Rate...................................................... -0.025898
Time accessing memory/Total time............................................ 0.312404
L1--L2 bandwidth used (MB/s, average per process)........................... 25.477978
Memory bandwidth used (MB/s, average per process)........................... 103.020665
MFLOPS (average per process)................................................ 0.524341
Cache misses in flight per cycle (average).................................. 0.922461
Prefetch cache miss rate.................................................... 0.183908
real 21.378
user 75.025
sys 0.339