24 cpus used
compiler option: -O3 -mp
24 cpu runs
WARNING: Multiplexing events to project totals--inaccuracy possible
Summary for execution of ./memory_locality_1
Based on 250 MHz IP27
MIPS R10000 CPU
CPU revision 3.x
Typical Minimum Maximum
Event Counter Name Counter Value Time (sec) Time (sec) Time (sec)
===================================================================================================================
0 Cycles...................................................... 212841990704 851.367963 851.367963 851.367963
16 Cycles...................................................... 212841990704 851.367963 851.367963 851.367963
14 ALU/FPU progress cycles..................................... 29181282400 116.725130 116.725130 116.725130
6 Decoded branches............................................ 23651040592 94.604162 94.604162 94.604162
2 Issued loads................................................ 20325179296 81.300717 81.300717 81.300717
18 Graduated loads............................................. 20322189744 81.288759 81.288759 81.288759
26 Secondary data cache misses................................. 101960720 30.792137 20.131125 34.258802
25 Primary data cache misses................................... 425802800 15.345933 4.803056 15.345933
21 Graduated floating point instructions....................... 3429469264 13.717877 6.858939 713.329607
7 Quadwords written back from scache.......................... 405805952 10.388632 6.866237 10.388632
3 Issued stores............................................... 1721026432 6.884106 6.884106 6.884106
19 Graduated stores............................................ 1719699696 6.878799 6.878799 6.878799
22 Quadwords written back from primary data cache.............. 426500464 6.568107 5.356846 7.591708
23 TLB misses.................................................. 517600 0.140974 0.140974 0.140974
9 Primary instruction cache misses............................ 596544 0.042999 0.013434 0.042999
10 Secondary instruction cache misses.......................... 118400 0.035757 0.023377 0.039782
24 Mispredicted branches....................................... 452656 0.002571 0.001159 0.009451
30 Store/prefetch exclusive to clean block in scache........... 394752 0.001579 0.001579 0.001579
31 Store/prefetch exclusive to shared block in scache.......... 21872 0.000087 0.000087 0.000087
4 Issued store conditionals................................... 2144 0.000009 0.000009 0.000009
5 Failed store conditionals................................... 912 0.000004 0.000004 0.000004
20 Graduated store conditionals................................ 640 0.000003 0.000003 0.000003
1 Issued instructions......................................... 68559314352 0.000000 0.000000 274.237257
8 Correctable scache data array ECC errors.................... 0 0.000000 0.000000 0.000000
11 Instruction misprediction from scache way prediction table.. 20432 0.000000 0.000000 0.000082
12 External interventions...................................... 339616 0.000000 0.000000 0.000000
13 External invalidations...................................... 2055536 0.000000 0.000000 0.000000
15 Graduated instructions...................................... 68216005952 0.000000 0.000000 272.864024
17 Graduated instructions...................................... 68568877440 0.000000 0.000000 274.275510
27 Data misprediction from scache way prediction table......... 2147648 0.000000 0.000000 0.008591
28 External intervention hits in scache........................ 297792 0.000000 0.000000 0.000000
29 External invalidation hits in scache........................ 512176 0.000000 0.000000 0.000000
Statistics
=========================================================================================
Graduated instructions/cycle................................................ 0.320501
Graduated floating point instructions/cycle................................. 0.016113
Graduated loads & stores/cycle.............................................. 0.103560
Graduated loads & stores/floating point instruction......................... 6.427201
Mispredicted branches/Decoded branches...................................... 0.000019
Graduated loads/Issued loads................................................ 0.999853
Graduated stores/Issued stores.............................................. 0.999229
Data mispredict/Data scache hits............................................ 0.006632
Instruction mispredict/Instruction scache hits.............................. 0.042732
L1 Cache Line Reuse......................................................... 50.765487
L2 Cache Line Reuse......................................................... 3.176145
L1 Data Cache Hit Rate...................................................... 0.980682
L2 Data Cache Hit Rate...................................................... 0.760545
Time accessing memory/Total time............................................ 0.157918
Time not making progress (probably waiting on memory) / Total time.......... 0.862897
L1--L2 bandwidth used (MB/s, average per process)........................... 24.019810
Memory bandwidth used (MB/s, average per process)........................... 22.955841
MFLOPS (average per process)................................................ 4.028187
real 38.025
user 850.931
sys 1.916